1. Field of the Invention
The present invention relates generally to display systems, such as electro-optic or liquid crystal display systems. The present invention also relates to a method for enhancing the performance of reflective flat-panel displays. In particular, the invention relates to a method for planarizing the backplane of an electro-optic device. More particularly, the invention relates to a method for planarizing LCOS backplanes using a spin-cast polymeric resin, and to a device including a spin-cast polymeric resin planarized backplane.
2. Background of the Related Art
LCOS SLM's and microdisplays are made by sandwiching a thin layer of electro-optic material between an array of silicon chip circuits and an indium tin oxide coated coverglass. Incoming optical wavefronts are modulated by applying a voltage differential across the liquid crystal layer. LCOS devices have been successfully applied to coherent optical processors for a range of applications, and can also be used in various incoherent applications, such as image projection and head-up display systems.
In planarizing a backplane of a LCOS, or a silicon backplane, a dielectric layer is formed above the device circuitry. The dielectric layer above the device circuitry should be as flat as possible. Such a flat dielectric layer formed above the device circuitry provides a number of benefits or advantages to SLM's intended for coherent optical processing, as will be described fully hereinbelow.
The planarization of the backplane of an LCOS device was previously attempted by applying polyimide as the planarizing dielectric to a one-metal PMOS backplane. Vias (ca. 37 .mu.m.) were wet-etched through the polyimide layer, and a Au-Ni alloy was evaporated to form a specular reflective mirror layer over the polyimide layer and in electrical contact with the first metal layer. (K. Kasahara, et al. (1980) 1980 IEEE Biennial Display Research Conference, 96-101).
The Degree of Planarization (DOP) may be used as a measure of the flatness or planarity of a surface, and may be used to compare the effectiveness of a planarization method, where DOP is given by the formula: ##EQU1## where t.sub.before is the step height of the surface before planarization, and t.sub.after is the step height after planarization. (See, for example, D. Burdeaux, et al. (1990) reference.) DOP values for polyimide planarization are typically in the range of only 18-30% (B. Merriman, et al. (1989) Proc. 39th ECC, 5). In addition to their relatively low DOP values, polyimide dielectric planarization layers are characterized by other problems, including water uptake and pinholing, leading to delamination of the planarizing layer and unintentional interconnection between metal layers. See, for example, N. Einspruch, et al. (Eds.) (1987) VLSI Electronics--Microstructure Science, Vol. 15, VLSI Metallization. The water uptake problem requires lengthy bake-out periods during processing. See, for example, D. Burdeaux, et al. (1990) J. Electronic Materials, 19: 1357-1366.
Chemical mechanical polishing (CMP) has also been used as a means for the planarization of the backplane of an LCOS device. According to CMP, a conformal dielectric layer, such as SiO.sub.2, which has been deposited on the structures surface (by PECVD) may be flattened with a rotating pad and polishing slurry. CMP can achieve an extremely flat surface (see, for example, A. O'Hara, et al. (1993) Applied Optics, 32: 5549-5556. However, CMP has a number of significant disadvantages, including long processing times, the need to control many process variables, and the requirement of expensive equipment.
The present invention solves a significant problem in the art by providing a simplified method for planarization of LCOS devices, the method having a number of advantages, as will be described fully hereinbelow.